This patent application claims priority based on a Japanese patent application, 2000-268061 filed on Sep. 5, 2000, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a time measuring device, a testing apparatus and a shift register. More particularly, the present invention relates to a time measuring device that can measure small time intervals between edges of a signal with high precision.
2. Description of the Related Art
As a conventionally known time measuring device for measuring a period of a rectangular wave, for example, U.S. Pat. No. 4,769,798 discloses an apparatus that converts a value of the period of an input signal into a voltage value and outputs the voltage value.
Semiconductor device operating speed has dramatically increased in recent years. In a semiconductor memory device, for example, an operating frequency of a xe2x80x9cRambusxe2x80x9d (registered trademark) DRAM (Dynamic Random Access Memory) exceeds 400 MHz. The period of a clock output from the Rambus DRAM is 2.5 ns or less and the measurement requires a precision of at least 10 ps.
The apparatus disclosed in the U.S. Pat. No. 4,769,798 performs an operation such as an analog operation or a sample-hold operation, for the input signal two times, so as to convert the period value of the input signal into the voltage value. Therefore, in order to measure the period of the clock of the Rambus DRAM by the conventional time measuring device, the operation has to be done within 2.5 ns, while the measurement precision is kept to at least 10 ps. In the conventional time measuring device, however, tradeoff relationship exists between the successive measurements and the measurement precision. Thus, the successive measurements of the period of the clock output from the Rambus DRAM with high precision were very difficult to obtain.
Therefore, it is an object of the present invention to provide a time measuring device, a testing apparatus and a shift register, which are capable of overcoming the above drawbacks accompanying the conventional art. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to the first aspect of the present invention, a time measuring device comprises: an input signal detecting unit operable to detect three or more edges in an input signal and to output three or more detection signals in parallel, the three or more detection signals changing based on the three or more edges, respectively; a converting unit operable to convert phase differences between change timings of the detection signals and clock edges in a reference clock having a predetermined operating frequency into analog voltage values, respectively; a counting unit operable to count, from change timings of at least two of the detection signals, numbers of the clock edges between the clock edges from which the at least two detection signals are respectively delayed by the phase differences corresponding to the at least two detection signals; an operating unit operable to calculate a time interval between edges of the three or more edges based on the analog voltage values and the numbers of clock edges.
The converting unit may output three or more timing signals that respectively change based on the clock edges; the counting unit may count, as the numbers of the clock edges, numbers of the clock edges between change timings of the three or more timing signals; a digital converting unit may be further provided to include an analog-digital converter operable to convert the analog voltage values into digital voltage values, respectively, and a voltage memory operable to store the digital voltage values; and the operating unit may calculate the time interval based on the numbers of clock edges and the digital voltage values.
The digital converting unit may include a selection unit operable to: receive the three or more timing signals; supply one of the analog voltage values that corresponds to one of the received timing signals, that was changed first, to the analog-digital converter; and select one of the analog voltage values that respectively corresponds to the remaining timing signals one by one other than the one timing signal that was changed first to supply the selected analog voltage values to the analog-digital converter one by one, based on an end of an operation for converting the analog voltage value that corresponds to the timing signal that was changed first into a corresponding digital voltage value by the analog-digital converter and changes of the timing signals.
The counting unit may include: a counter operable to count the number of clock edges; and a clock memory operable to store the number of clock edges counted by the counter. In this case, the received timing signals indicate addresses in the clock memory at which the number of clock edges corresponding to the received timing signals in accordance with an order in which the timing signals were received.
The counting unit may further include an address encoder operable to encode the addresses based on changes of the received timing signals.
The counting unit may count, as the number of clock edges, number of clock edges between a change timing of the one timing signal that changed first and change timings of the other timing signals than the one timing signal and stores the counted number of clock edges in the clock memory.
The operating unit may read the digital voltage values stored in the voltage memory and the number of clock edges stored in the clock memory to calculate the time interval.
The input signal detecting unit may include: a first shift register operable to output positive detection signals as the detection signals that change based on positive edges in the input signal, the positive edges being edges at which the input signal changes from logical L to logical H; and a second shift register operable to input an inverted input signal obtained by inverting the input signal and to output negative detection signals as the detection signals that change based on negative edges in the input signal, the negative edges being edges at which the inverted input signal changes from logical L to logical H, and wherein the three or more detection signals are output in parallel.
Each of the first and second shift registers may be a shift register including a plurality of flip-flops connected to each other, each flip-flop having a data input and a trigger input. Moreover, each of the flip-flops other than a last one of the flip-flops may supply data input to the data input thereof to the data input of a next flip-flop in accordance with an edge change in the input signal or inverted input signal that is input to the trigger input thereof, while the last flip-flop supplies data obtained by inverting the data input to the data input thereof to the data input of the first flip-flop in accordance with the edge change.
The converting unit may include: a first time-voltage converting unit operable to receive the positive detection signals, convert phase differences between change timings of the positive detection signals and the clock edges in the reference clock into positive analog voltage values as the analog voltage values, and output positive timing signals as the timing signals that change based on the clock edges and the positive analog voltage values; and a second time-voltage converting unit operable to receive the negative detection signals, convert phase differences between change timings of the negative detection signals and the clock edges in the reference clock into negative analog voltage values as the analog voltage values, and output negative timing signals as the timing signals that change based on the clock edges and the negative analog voltage values.
The digital converting unit may include a first digitizing unit and a second digitizing unit, the first voltage digitizing unit includes: a first selection unit as the selection unit operable to receive the positive analog voltage values and the positive timing signals and to select one of the positive analog voltage values to be converted into one of the corresponding digital voltage values; a first analog-digital converter as the analog-digital converter operable to convert the selected positive analog voltage value into a corresponding positive digital voltage value; and a first voltage memory as the voltage memory operable to store the positive digital voltage values. Moreover, the second voltage digitizing unit may include: a second selection unit as the selection unit operable to receive the negative analog voltage values and the negative timing signals and to select one of the negative analog voltage values to be converted into one of the corresponding digital voltage values; a second analog-digital converter as the analog-digital converter operable to convert the selected negative analog voltage value into a corresponding negative digital voltage value; and a second voltage memory as the voltage memory operable to store the negative digital voltage values.
The counting unit may include: a first clock counting unit having a first counter as the counter operable to receive the positive timing signals and to count the number of clock edges between change timings of the positive timing signals, and a first clock memory as the clock memory operable to store the number of clock edges counted by the first counter; and the second clock counting unit having a second counter as the counter operable to count the number of clock edges between change timings of the negative timing signals, and a second clock memory as the clock memory operable to store the number of clock edges counted by the second counter. Moreover, the change of the received positive timing signals may indicate addresses in the first clock memory at which the counted number of clock edges respectively corresponding to the received positive timing signals are stored, in accordance with an order in which the changes of the positive timing signals were received, and the change of the received negative timing signals may indicate addresses in the second clock memory at which the counted number of clock edges respectively corresponding to the received negative timing signals are stored, in accordance with an order in which the changes of the negative timing signals were received.
The time measuring device may further comprise an edge-difference counting unit operable to count a number of clock edges between a change timing of at least one of the positive timing signals and a change timing of at least one of the negative timing signals.
The edge-difference counting unit may count a number of clock edges between a change timing of one of the positive timing signals, that changed first after the first shift register was reset, and a change timing of one of the negative timing signals, that changed first after the second shift register was reset.
The first voltage digitizing unit may output a positive end signal that changes after all the positive digital values to be stored in the first voltage memory have been stored, while the second voltage digitizing unit outputs a negative end signal that changes after all the negative digital values to be stored in the second voltage memory have been stored. Moreover, the operating unit, after receiving a change of an end signal based on the positive end signal and the negative end signal, may read data from the first voltage memory, the second voltage memory, the first clock memory, the second clock memory and the edge-difference counting unit to calculate the time interval.
According to the second aspect of the present invention, a testing apparatus for testing an electronic device, comprises: a pattern generator operable to generate an input pattern signal to be input to the electronic device; a signal inputting/outputting unit operable to supply the input pattern signal to the electronic device while being in electric contact with the electronic device, and to receive an output pattern signal output from the electronic device based on the input pattern signal; and a detecting unit operable to detect the output pattern signal output from the electronic device, wherein the detecting unit includes: an input signal detecting unit operable to detect three or more edges in the output pattern signal and to output detection signals in parallel, the detection signals changing based on the three or more edges, respectively; a converting unit operable to convert phase differences between change timings of the detection signals and clock edges in a reference clock having a predetermined operating frequency into analog voltage values, respectively; a counting unit operable to count, from change timings of at least two of the detection signals, number of clock edges between the clock edges from which at least two detection signals are respectively delayed by the phase differences; and an operating unit operable to calculate a time interval between edges of the three or more edges based on the analog voltage values and the number of clock edges.
The testing apparatus may further comprise: a first transmission line, which connects the signal inputting/outputting unit with the converting unit electrically, operable to transmit the three or more detection signals; and a second transmission line, which connects the signal inputting/outputting unit with the input signal detecting unit electrically, operable to transmit the output pattern signal, wherein a transmission distance of the output pattern signal transmitted in the second transmission line is shorter than a transmission distance of one of the three or more detecting signal transmitted in corresponding the first transmission line. In this case, it is preferable that the first transmission line is a coaxial cable.
The testing apparatus may further comprise: a first transmission line, which connects the signal inputting/outputting unit to the converting unit electrically, operable to transmit the three or more detection signals; and a second transmission line, which connects the signal inputting/outputting unit to the input signal detecting unit electrically, operable to transmit the output pattern signal, wherein a signal time delay of the output pattern signal in the second transmission line is shorter than a signal time delay of one of the three or more detecting signal in the first transmission line. In this case, it is preferable that the first transmission line is a coaxial cable.
The summary of the invention does not necessarily describe all necessary features of the present invention. The present invention may also be a sub-combination of the features described above. The above and other features and advantages of the present invention will become more apparent from the following description of the embodiments taken in conjunction with the accompanying drawings.